1. Field of the Invention
The present invention relates to a semiconductor device with a contact hole extending through a wiring layer on a semiconductor substrate and electrically connecting an upper layer and a lower layer of the wiring layer, and a fabrication process therefor.
2. Description of the Prior Art
FIG. 1 is an equivalent circuit diagram showing a general static memory cell (SRAM cell). As shown in FIG. 1, the SRAM cell formed on a semiconductor substrate as a semiconductor device is constructed with two high resistance load elements (load resistors R1 and R2) and four N-channel MOS transistors T1, T2, T3 and T4. Among these MOS, transistors consisting of a pair of driving MOS transistors T1 and T2, a drain of one transistor is connected to a gate of the other transistor, and is connected to one end of the load resistor R1 or R2. Namely, the drain of the MOS transistor T1 is connected to the gate of the MOS transistor T2 and one end of the load resistor R1. On the other hand, the drain of the MOS transistor T2 is connected to the gate of the MOS transistor T1 and one end of the load resistor R2. Sources of respective MOS transistors T1 and T2 are fixed to a grounding potential V.sub.ss. By this, a flip-flop circuit is constructed.
A power source voltage V.sub.cc is applied on the other ends of the load resistors R1 and R2. By this, a fine current may be supplied to the flip-flop circuit. Also, accumulation nodes N1 and N2 of the flip-flop circuit are respectively connected to the drains or sources of the transfer MOS transistors T3 and T4. The sources or drains of the transfer MOS transistors T3 and T4 are connected to two data lines 2a and 2b extending in parallel. Furthermore, one word line 1a extending perpendicular to the data lines 2a and 2b is connected to gates of the transfer MOS transistors T3 and T4. By this, a one-bit memory cell is constructed.
In the SRAM cell constructed as set forth above, a plate form grounding wiring (grounding potential V.sub.ss) is formed over the entire surface of the cell. When resistance of the grounding wiring is reduced, the flip-flop circuit of the cell can be operated stably at low voltage. As a technology for forming the plate form grounding wiring, contact formation technology is known (Japanese Unexamined Patent Publication (Kokai) No. Heisei 2-285658.
FIGS. 2A to 2D are sections showing sequential process steps of conventional fabrication process of the semiconductor device utilizing contact forming technology. As shown in FIG. 2A, at first, a P-type well layer 2 is formed by ion implantation of boron in the surface of the semiconductor substrate 1 and by thermal diffusion. Next, a field oxide layer 3 in a thickness of 1000 to 5000 .ANG. thick is selectively formed on the surface of the P-type well layer 2 by using LOCOS method. By this, an element region is defined. Subsequently, a gate oxide layer 4 is formed in a thickness of 100 to 300 .ANG. on the surface of the element region (P-type well layer 2).
Thereafter, an opening portion 7 is selectively formed through the gate oxide layer 4. Then, a conductive layer (not shown) of a polycrystalline silicon or the like is formed over the entire surface in a thickness of 1000 to 3000 .ANG.. A gate electrode 5a of a driving MOS transistor and gate electrodes 5b of transfer MOS transistors are formed by selectively removing the conductive layer through photolithographic and dry etching. Subsequently, with taking the gate electrodes 5a and 5b as a mask, ion implantation of arsenic is performed over the entire surface to form a N-type impurity diffusion layer 6 on the surface of the P-type well layer 2. After formation of a first interlayer insulation layer 8 over the entire surface, a grounding wiring layer 9 of polycrystalline silicon, tungsten silicide or the like is formed in a thickness of 1000 to 2000 .ANG. on the first interlayer insulation layer 8. Thereafter, a second interlayer insulation layer 10 is formed in a thickness of 1000 to 2000 .ANG. on the surface of the grounding wiring layer 9.
Then, as shown in FIG. 2B, selectively removing the first interlayer insulation layer 8, the grounding wiring layer 9 and the second interlayer insulation layer 10 formed on the gate electrode 5a of the driving MOS transistor, a first contact hole 11 is provided. By this, a part of the surface of the gate electrode 5a is exposed. Subsequently, a silicon oxide layer 12 is formed in a thickness of 500 to 2000 .ANG. on the inner periphery of the first contact hole 11 (on the side wall surface and the bottom wall surface of the contact hole) and on the upper surface of the second interlayer insulation layer 10.
Thereafter, as shown in FIG. 2C, the silicon oxide layer 12 located on the upper surface of the second interlayer insulation layer 10 and on the bottom wall surface of the contact hole 11 is removed by way of anisotropic etching, to remain only silicon oxide layer 12 on the side wall surface of the first contact hole 11. By this, a first side wall insulation layer 13 is formed. Thereafter, on the inner peripheral surface of the first contact hole 11 and on the second interlayer insulation layer 10, a polycrystalline silicon layer (not shown) is formed in a thickness of 500 to 1500 .ANG.. The polycrystalline silicon layer is then doped with phosphorous in a concentration of 1.times.10.sup.13 to 1.times.10.sup.14 (/cm.sup.2) by way of ion implantation. Then, the polycrystalline silicon layer is patterned by photolithographic and dry etching to form a load resistor 14. Subsequently, ion implantation of phosphorous is performed into a desired position in the load resistor 14, in a concentration of 1.times.10.sup.15 to 1.times.10.sup.16 (/cm.sup.2) to form a power source wiring portion (V.sub.cc) 15.
Thereafter, as shown in FIG. 2D, a third interlayer insulation layer 16 is formed over the entire surface. In conjunction therewith, the first contact hole is varied to planarize the surface by the third interlayer insulation layer 16. Subsequently, the first interlayer insulation layer 8, the grounding wiring layer 9 and the second interlayer insulation layer 10 are selectively removed by way of photolithographic and dry etching, to provide a second contact hole 17. By this, a part of the surface of the N-type impurity diffusion layer 6 is exposed. Thereafter, on the inner peripheral surface of the second contact hole 17 (on the side wall surface and on the bottom wall surface of the second contact hole 17) and the upper surface of the third interlayer insulation layer 16, a silicon oxide layer (not shown) is formed in a thickness of 500 to 2000 .ANG..
Thereafter, the silicon oxide layer located on the upper surface of the third interlayer insulation layer 16 and on the bottom wall surface of the contact hole 17 is removed by anisotropic etching, to leave only silicon oxide layer on the side wall surface of the second contact hole 17. By this, a second side wall insulation layer 18 is formed. Thereafter, over the entire surface, a conductive layer (not shown) of aluminum or so forth is formed in a thickness of 2000 to 10000 .ANG.. In conjunction therewith, the second contact hole is varied by the conductive layer. Then, the conductive layer is patterned by photolithographic and dry etching into the predetermined shape to form a data line 19.
In the semiconductor device constructed as set forth above, since the grounding wiring layer 9 is formed over substantially entire surface on the semiconductor substrate 1, resistance of the grounding wiring layer 9 can be reduced. Thus, the flip-flop circuit can be operated stably at low voltage. Also, while the contact holes 11 and 17 are provided through the grounding wiring layer 9, since the side wall insulation layers 13 and 18 are formed on the side wall surface of the contact holes, shorting between the conductive material filled in the contact holes and the grounding wiring layer 9 can be certainly prevented.
However, when the semiconductor device is fabricated through the conventional process, the following problems should be encountered. The first problem is that the process is complicated and includes a large number of process steps. The reason is that the side wall insulative layers 13 and 18 have to be formed by anisotropic etching of the silicon oxide layers separately upon formation of two different contact holes 11 and 17.
The second problem is that fabrication of masks for providing the contact holes 11 and 17 is complicated. The reason is that the positions to provide the contact holes have to be defined precisely. If the precision of positioning is low, it becomes not possible to provide the contact holes at only on the electrodes to make the contact hole to cause interference with the adjacent electrode located adjacent the desired electrode to cause shorting between the electrodes.